The present invention relates to verification or simulation of a design using behavioral models structured in a Client/Server configuration. Each model consists of a physical part which presents the external interface, and a functional part which stores the state of the model and presents an internal procedural interface. A testcase is a set of procedure calls which exercise such models written in VHDL.
Logic verification is a large and growing component of an ASIC design and development effort. Based on the experiences of past design efforts, it has become immensely clear that the number of testcases written during the course of a project (on the order of hundreds) far out numbers the total number of behavioral models (on the order of tens) which comprise a typical testbench. A large fraction of all verification resource is consumed in writing and debugging the large set of testcases. This impacts directly the quality of logic verification achievable with in the project resource constraints.
A system, method and computer program features of the present invention, relate to verification or simulation of a design using behavioral models structured in a Client/Server configuration. Each model consists of a physical part which presents the external interface, and a functional part which stores the state of the model and presents an internal procedural interface. A testcase is a set of procedure calls which exercise such models, written in VHDL. The present invention describes the architecture and implementation of a client/server behavioral model and procedural approach for testcase development which results in significant gain in productivity, quality of logic verification, and portability.